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| SL2150F Front end power splitter with AGC Datasheet DS5535 ISSUE 1.6 November 2001 Features * Single chip quadruple power splitter (primary channel, secondary channel, OOB channel and loop through) Wide dynamic range on all channels Independent AGC facility incorporated into all channel paths CSO, CTB, CXM all better than -62dBc for +3dBmV agc attack point Full ESD protection. (Normal ESD handling procedures should be observed) Ordering Information SL2150F/KG/LH2S (tubes) SL2150F/KG/LH2T (tape and reel) * * * * Applications * * * Multi-tuner cable set top box and cable modem applications Data communications systems Terrestrial TV tuner loop though Vee Vee RFOUT4 RFOUT4B Vcc Vcc Vcc RFOUT1B RFOUT1 NC# NC# NC# RFOUT2 RFOUT2B SL2150F 1 Vcc Vcc RF INPUT RF INPUT Vee AGC1 AGC2 Vee Vee RFOUT3 RFOUT3B NC# AGC4 AGC3 Description The SL2150F is a wide dynamic range single chip power splitter for cable set top box multi-tuner applications. The device offers four buffered outputs from a single input. VEE (PACKAGE PADDLE) LH28 # Pins marked NC should be connected to Vee All signal paths contain controllable AGC facility. an independently Figure 1 - Pin allocation AGC1 AGC2 AGC3 AGC4 AGC CONTROL RFOUT1 RFOUT1B AGC CONTROL RFOUT2 RFOUT2B RFINPUT RFINPUTB power splitter AGC CONTROL RFOUT3 RFOUT3B AGC CONTROL RFOUT4 RFOUT4B Figure 2 - SL2150F block diagram 1 SL2150F Datasheet Quick Reference Data NB all data applies with differential termination and single ended source both of 75 Characteristic RF input operating range Conversion gain, with external load as in figure (12) maximum minimum Input NF, all signal paths at maximum conversion gain IPIP3, all paths IPIP2, all paths CTB * CSO * CXM * Input impedance Input VSWR Output impedance differential, all loops (requires external load for example as in figure (12) Input to output isolation (all loops) Output to output isolation (all loops) 5.5 -25 7 127 151 -66 -64 -66 75 8 440 30 25 dB dB dB dBV dBV dBc dBc dBc dB dB dB 50-860 Units MHz * 132 channel matrix at +15 dBmV per channel, 75 source impedance, all paths, max gain 2 Datasheet Functional Description The SL2150F is a broadband wide dynamic range power splitter with AGC and is optimised for application in multi tuner cable set top box applications. It also has application in any system where a wide dynamic range broadband power splitter is required. The pin assignment is contained in figure (1) and the block diagram in figure (2). The port internal peripheral circuits are contained in figure (14) In normal application the RF input is interfaced to the device input. The input preamplifier is designed for low noise figure, within the operating region of 50 to 860 MHz and for high intermodulation distortion intercept so offering good signal to noise plus composite distortion spurious performance when loaded with a multi carrier system. The preamplifier when combined with the input network shown in figure (3) provides an impedance match to a 75 source. The typical impedance is shown in figure (4). The input NF and input referred two-tone intermodulation test condition spectrum are shown in figures (5) and (6) respectively. The output of the preamplifier is then power split to four independently controlled AGC stages. Each AGC stage provides for a minimum of 30 dB of gain control across the input frequency range. The typical AGC characteristic and NF versus gain setting are contained in figures (7) and (8) respectively. SL2150F The input referred third order intercept point is independent of gain setting. Finally each of the AGC stages drive an output buffer of nominal differential output impedance of 440, which provides a nominal 5.5 dB of conversion gain when terminated into a differential 75 load. In application it is important to avoid saturation of the output stage, therefore it is recommended that the output standing current be sunk to Vcc through an inductor. A resistive pull up can also be used as shown in figure (13b), however the resistor values should not exceed 38 ohm single ended. If an inductive current sink is used the maximum available gain from the device is circa 20 dB. This gain can be reduced by application of an external load between the differential output ports. The gain can be approximately calculated from the following formula; GAIN = 20*log ((Parallel combination of 440 ohm and external load between ports) / 44 ohm) + 2dB For example when driving a 200 ohm load as in figure (13a), the gain equals; Gain = 20 *log ((440 * 200)/(440+200)/44) +2dB = 12dB 3 SL2150F Datasheet 1nF 3 RF INPUT RFIN F TYPE 1nF 5.1nH MABAES0029 1:1 4 RF INPUTB SL2150F Figure 3 - RF input matching network 16 Nov 2001 10:10:47 55.758 10.44 nH 850.000 000 MHz PRm Cor Avg 16 Smo CH1 S11 1 U FS 4_: 133.23 Z0 75 1_: 169.02 -44.117 50 MHz 2_: 49.916 -57.436 250 MHz 3_: 31.238 -5.5576 500 MHz 4 3 1 2 START 50.000 000 MHz STOP 850.000 000 MHz Figure 4 - Typical single-ended RF input impedance with input match Input NF vs Frequency @25DegC (With Matching Network) 10.0 9.0 8.0 7.0 6.0 NF (dB) 5.0 4.0 3.0 2.0 1.0 0.0 0 100 200 300 400 Frequency (MHz) 500 600 700 800 900 Figure 5 - Input NF at 25 deg C 4 Datasheet SL2150F -15 dBm INCIDENT POWER FROM 75 SOURCE IIM2; -57dBc IIM3 -66dBc -72 dBm -81 dBm df f2-f1 f1-df f1 f2 f2+df Figure 6 - Two tone intermodulation test condition spectrum, input referred 0 0 0.5 1 1.5 2 2.5 3 -10 Back off from maximum gain setting (dB) -20 -30 -40 -50 -60 -70 AGC input voltage (V) Figure 7 - Typical AGC versus control voltage characteristic 5 SL2150F Datasheet Typical Variation in NF vs Gain Setting (With Matching Network) 50.0 40.0 30.0 NF (dB) 20.0 10.0 0.0 -40.0 -35.0 -30.0 -25.0 -20.0 -15.0 Gain (dB) -10.0 -5.0 0.0 5.0 10.0 Figure 8 - Typical variation in NF versus gain setting 132 channel matrix, 75Ohm source, all channels at +15 dbmV. Input and ouput conditions as in Fig 3 and Fig 12. -50 -55 -60 CSO, CTB (dBC) -65 CSO (dBC) CTB (dBC) -70 -75 -80 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 Back off from maximum gain (dB) Figure 9 - Typical variation in CSO and CTB versus back off from maximum gain Driven output stage 50 C Directional coupler A Port 1 Network Analyser D Monitored output stage B C Directional coupler A Port 2 D B 50 Directional coupler phase relationship AB C00 D 180 0 Figure 10 - Test condition for output crosstalk 6 Datasheet SL2150F Driven output stage 50 C Directional coupler A Port 1 Network Analyser Port 2 D Monitored input stage B Directional coupler phase relationship AB C00 D 180 0 Figure 11 - Test condition for output to input crosstalk Vcc 100n 100p SL2150F MABAES0029 1:1 To 75 load 1nF FTYPE Figure 12 - Example application driving 75 load Vcc 10H 10H 1nF SL2150F 1nF 200 Figure 13a - Example application driving 200 load with inductive pull up 7 SL2150F Datasheet Vcc 2x 38 1nF SL2150F 1nF Note: External resistor values must not exceed 38 200 Figure 13b - Example application driving 200 load with resistive pull up Vcc INPUT INPUT DECOUPLE 1 k 2.5V 220 220 OUTPUT 2.5V 270 1 k 3.9V 16 mA 16 mA Output ports 30 k RF input port AGC INPUT 1.6V 1.5 k AGC port Figure 14 - Port peripheral circuitry 8 Datasheet Electrical Characteristics SL2150F Test conditions (unless otherwise stated) Tamb = -40 to 85C, Vee= 0V, Vcc=5V+-5% These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Supply current Input frequency range Input impedance Input return loss 3,4 50 75 8 pin min typ 190 max 228 860 units mA MHz dB See figure (4) Conditions Input Noise Figure 8 dB Tamb=27C, see figure (5) All loops at maximum conversion gain See figure (8) Power gain from 75 single ended source to differential 75 load Variation in NF with gain adjust Gain -1 dB/dB maximum minimum minimum 4 5.5 7 -25 dB dB dB Vagcip=3.0V Vagcip=0.5V Vagcip=Vee AGC monotonic from Vee to Vcc Refer to 'Functional description' section for information on calculating maximum gain with other load conditions -65 Input referred IP2 Input referred IP3 Input referred IM2 42 18 -57 -37 dBm dBm dBc dBc dBc dBc dBc dBc dBc Assuming ideal power match. See note (2) and figure (6) Assuming ideal power match. See note (2) and figure (6) See note (2) and figure (6) See note (3) and figure (6) See note (2) and figure (6) See note (3) and figure (6) All gain settings See note (4) and figure (9) See note (4) See note (4) Input referred IM3 -66 -46 CSO CTB CXM -62 -64 -64 9 SL2150F Characteristic Input P1dB Datasheet pin min typ +9 0.25 max units dBm dB Conditions All gain settings, with load as in figure (12) Channel bandwidth 8 MHz within operating frequency range, all loops, all gain settings Differential Gain variation within channel Output impedance 11,12 15,16 20,21 24,25 11,12 15,16 20,21 24,25 6,7 8,9 -150 440 Output port DC standing current 25 mA Standing current that any external load has to sustain AGC input leakage current Crosstalk between all loop outputs 150 -25 A dB Vagcip = Vee to Vcc, all control inputs All gain settings, measured differential output to differential output, driven ports in phase and monitored ports out of phase, see figure (10) All gain settings, measured differential output to single ended input, driven ports in phase, see figure (11) Crosstalk between all loop outputs and RF input -30 dB Notes (1) All power levels are referred to 75 and 0 dBm = 109 dBV (2) Any two tones within RF operating range at -15 dBm, from single-ended 75 ohm source into differential 75 load as in figure (12), gain setting between maximum and -15dB backoff. (3) Any two tones within RF operating range at -5 dBm, from single-ended 75 ohm source into differential 75 load as in figure (12) (4) Load as in figures (12) & (13), max gain, 132 channel matrix, 75 ohm source with all channels at +15 dBmV, assuming power match 10 Datasheet Absolute Maximum Ratings All voltages are referred to Vee at 0V Characteristic Supply voltage RF input voltage All I/O port DC offsets Storage temperature Junction temperature Package thermal resistance, chip to ambient Power consumption at 5.25V ESD protection 1.5 -0.3 -55 min -0.3 max 6 8 Vcc+0.3 150 125 35 1200 units V dBm V C C C/W mW kV Power applied Differential conditions SL2150F Paddle to be soldered to ground plane Mil-std 883B method 3015 cat1 Evaluation Board Figures 15 and 16 show schematic and PCB layout for a 4 layer evaluation board. 11 SL2150F 2 1 Vcc 28 27 26 25 24 23 22 Vcc Vcc Vcc RFOUT4B RFOUT4 Vee Vee AGC3 AGC4 Vee RFOUT3B RFOUT3 Vee Vee C13 100nF C10 C14 C15 100nF 1 2 3 4 5 C12 C16 C17 MOLEX5 100nF 100nF 100nF 100nF 100nF 8 9 10 11 12 13 14 12 PL1 MOLEX2 5 C1 100nF C2 MABAES0029 4 100nF 100nF 100nF C6 100nF 100nF IC 1 CNR Corner TX2 MABAES0029 4 1 Vcc 3 TX3 MABAES0029 1 PAD C25 1nF SK4 FTYPE 4 5 5 TX5 4 C19 1nF 1 C20 1nF 3 5 MABAES0029 Paddle SL2150F 3 Vcc C31 100pF C8 100nF C7 1 C5 100nF C30 100pF Vcc C27 470nF C3 C4 TX1 3 C23 1nF SK2 FTYPE C24 1nF SK3 FTYPE 1 2 3 4 5 6 7 Vcc Vcc RFINPUTB RFINPUT Vee AGC1 AGC2 RFOUT1B RFOUT1 Vee Vee Vee RFOUT2 RFOUT2B 21 20 19 18 17 16 15 C9 100nF C32 100pF C11 100nF Vcc 3 TX4 MABAES0029 1 4 C26 1nF SK5 FTYPE 5 C33 100pF C18 100nF PL2 Datasheet L1 SK1 FTYPE 5.1nH Figure 15 - SL2150F evaluation PCB Schematic Datasheet SL2150F Top view Layer2 view Layer3 view Bottom view mirrored Figure 16 - SL2150F evaluation PCB layout 13 http://www.zarlink.com World Headquarters - Canada Tel: +1 (613) 592 0200 Fax: +1 (613) 592 1010 North America - West Coast Tel: (858) 675-3400 Fax: (858) 675-3450 North America - East Coast Tel: (978) 322-4800 Fax: (978) 322-4888 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink Semiconductor's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001, Zarlink Semiconductor Inc. All rights reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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